At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are looking for a highly motivated PhD candidate to join the TIRAMISU project (Training and Innovation in Reliable and Efficient Chip Design for Edge AI, https://tiramisu-project.eu/).

The research will focus on the functional safety aspects of AI accelerators, aligned with ISO 26262 standards and utilizing state-of-the-art EDA tools. The PhD work will involve identifying safety-critical components of AI accelerators and developing advanced safety analysis methodologies.

The goal is to develop safety mechanisms and optimize safety verification techniques, including simulation-based fault injection and formal verification, to enhance the safety of AI hardware. These methods will be integrated into Cadence’s functional safety toolchain, contributing to a novel methodology that improves safety verification processes and accelerates time-to-market for AI accelerators.

Required qualifications:

  • MSc (or equivalent) in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline
  • Solid understanding of digital IC design and verification methodologies
  • Proficiency in hardware description languages (e.g., Verilog, VHDL) and programming
  • A background in functional safety is desirable

Requirements:

Benefits we offer you:

  • Competitive Salary
  • 30 days annual leave
  • Meal vouchers
  • Capital Forming Payment (VwL)
  • Ticket for the public transport
  • Working in a hybrid model in a modern office concept

And so much more, do not hesitate to contact us.

We’re doing work that matters. Help us solve what others can’t.

Location

FELDKIRCHEN 01 (Munich), Germany

Job Overview
Job Posted:
4 days ago
Job Expires:
Job Type
Full Time

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